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axivdma
Xilinx SDK Drivers API Documentation
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This example demonstrates how to use the AXI Video DMA with other video IPs to do video frame transfers.
This example does not work by itself. It needs two other Video IPs, one for writing video frames to the memory and one for reading video frames from the memory.
To see the debug print, you need a Uart16550 or uartlite in your system, and please set "-DDEBUG" in your compiler options. You need to rebuild your software executable.
MODIFICATION HISTORY:
Ver Who Date Changes
----- ---- -------- -------------------------------------------------------
1.00a jz 07/26/10 First release
1.01a jz 09/26/10 Updated callback function signature
2.00a jz 12/10/10 Added support for direct register access mode, v3 core
2.01a rvp 01/22/11 Renamed the example file to be consistent
Added support to the example to use SCU GIC interrupt
controller for ARM, some functions in this example have
changed.
rkv 03/28/11 Updated to support for frame store register.
3.00a srt 08/26/11 Added support for Flush on Frame Sync Feature.
4.00a srt 03/06/12 Modified interrupt support for Zynq.
4.02a srt 09/25/12 Fixed CR 677704
Description - Arguments misused in function
XAxiVdma_IntrEnable().
4.03a srt 03/01/13 Updated DDR base address for IPI designs (CR 703656).
6.2 ms 01/23/17 Modified xil_printf statement in main function to
ensure that "Successfully ran" and "Failed" strings
are available in all examples. This is a fix for
CR-965028.
Functions | |
| int | main (void) |
| Main function. More... | |
| int main | ( | void | ) |
Main function.
This function is the main entry point of the example on DMA core. It sets up DMA engine to be ready to receive and send frames, and start the transfers. It waits for the transfer of the specified number of frame sets, and check for transfer errors.