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dprxss
Xilinx SDK Drivers API Documentation
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Data Structures | |
| struct | XDpRxSs_Dp159Data |
| DP159 data structure. More... | |
Macros | |
| #define | XDPRXSS_DP159_IIC_SLAVE 0x5E |
| DP159 slave device address. More... | |
| #define | XDPRXSS_DP159_RBR 0x06 |
| 1.62 Gbps link rate More... | |
| #define | XDPRXSS_DP159_HBR 0x0A |
| 2.70 Gbps link rate More... | |
| #define | XDPRXSS_DP159_HBR2 0x14 |
| 5.40 Gbps link rate More... | |
| #define | XDPRXSS_DP159_LANE_COUNT_1 1 |
| Lane count of 1. More... | |
| #define | XDPRXSS_DP159_LANE_COUNT_2 2 |
| Lane count of 2. More... | |
| #define | XDPRXSS_DP159_LANE_COUNT_4 4 |
| Lane count of 4. More... | |
| #define | XDPRXSS_DP159_CPI_PD_RBR 0x1F |
| CPI pull down RBR. More... | |
| #define | XDPRXSS_DP159_CPI_PD_HBR 0x27 |
| CPI pull down HBR. More... | |
| #define | XDPRXSS_DP159_CPI_PD_HBR2 0x5F |
| CPI pull down HBR2. More... | |
| #define | XDPRXSS_DP159_PLL_CTRL_PD_RBR 0x30 |
| PLL control pull down RBR. More... | |
| #define | XDPRXSS_DP159_PLL_CTRL_PD_HBR 0x30 |
| PLL control pull down HBR. More... | |
| #define | XDPRXSS_DP159_PLL_CTRL_PD_HBR2 0x30 |
| PLL control pull down HBR2. More... | |
| #define | XDPRXSS_DP159_EQ_LEV 8 |
| Equivalisation level. More... | |
| #define | XDPRXSS_DP159_LOCK_WAIT 512 |
| Lock wait value. More... | |
Enumerations | |
| enum | XDpRxSs_Dp159ConfigType { XDPRXSS_DP159_CT_TP1 = 1, XDPRXSS_DP159_CT_TP2, XDPRXSS_DP159_CT_TP3, XDPRXSS_DP159_CT_UNPLUG } |
| This typedef enumerates the types of configuration types applied to DP159 to configure. More... | |