![]() |
rgb2ycrcb
Xilinx SDK Drivers API Documentation
|
Macros | |
| #define | XRGB2YCRCB_HW_H_ |
| Prevent circular inclusions by using protection macros. More... | |
| #define | XRgb2YCrCb_In32 Xil_In32 |
| Input operation. More... | |
| #define | XRgb2YCrCb_Out32 Xil_Out32 |
| Output operation. More... | |
| #define | XRgb2YCrCb_ReadReg(BaseAddress, RegOffset) XRgb2YCrCb_In32((BaseAddress) + (u32)(RegOffset)) |
| This function macro reads the given register. More... | |
| #define | XRgb2YCrCb_WriteReg(BaseAddress, RegOffset, Data) XRgb2YCrCb_Out32((BaseAddress) + (u32)(RegOffset),(u32)(Data)) |
| This function macro writes the given register. More... | |
Control Registers | |
Control registers offset for RGB2YCRCB core. | |
| #define | XRGB_CONTROL_OFFSET 0x000 |
| Control offset. More... | |
| #define | XRGB_STATUS_OFFSET 0x004 |
| Status offset. More... | |
| #define | XRGB_ERROR_OFFSET 0x008 |
| Error offset. More... | |
| #define | XRGB_IRQ_EN_OFFSET 0x00C |
| IRQ Enable offset. More... | |
| #define | XRGB_VERSION_OFFSET 0x010 |
| Version offset. More... | |
| #define | XRGB_SYSDEBUG0_OFFSET 0x014 |
| System Debug 0 offset. More... | |
| #define | XRGB_SYSDEBUG1_OFFSET 0x018 |
| System Debug 1 offset. More... | |
| #define | XRGB_SYSDEBUG2_OFFSET 0x01C |
| System Debug 2 offset. More... | |
Timing Control Registers | |
Timing control registers offset for RGB2YCRCB core. | |
| #define | XRGB_ACTIVE_SIZE_OFFSET 0x020 |
| Active Size (V x H) offset. More... | |
Core Specific Registers | |
Core specific registers offset. | |
| #define | XRGB_YMAX_OFFSET 0x100 |
| Luma Clipping offset. More... | |
| #define | XRGB_YMIN_OFFSET 0x104 |
| Luma Clamping offset. More... | |
| #define | XRGB_CBMAX_OFFSET 0x108 |
| Cb Clipping offset. More... | |
| #define | XRGB_CBMIN_OFFSET 0x10C |
| Cb Clamping offset. More... | |
| #define | XRGB_CRMAX_OFFSET 0x110 |
| Cr Clipping offset. More... | |
| #define | XRGB_CRMIN_OFFSET 0x114 |
| Cr Clamping offset. More... | |
| #define | XRGB_YOFFSET_OFFSET 0x118 |
| Luma Offset offset. More... | |
| #define | XRGB_CBOFFSET_OFFSET 0x11C |
| Cb Offset offset. More... | |
| #define | XRGB_CROFFSET_OFFSET 0x120 |
| Cr Offset offset. More... | |
| #define | XRGB_ACOEF_OFFSET 0x124 |
| A Coefficient offset. More... | |
| #define | XRGB_BCOEF_OFFSET 0x128 |
| B Coefficient offset. More... | |
| #define | XRGB_CCOEF_OFFSET 0x12C |
| C Coefficient offset. More... | |
| #define | XRGB_DCOEF_OFFSET 0x130 |
| D Coefficient offset. More... | |
Control Register Bit Masks | |
Control Register bit definition for RGB2YCRCB core. | |
| #define | XRGB_CTL_SW_EN_MASK 0x00000001 |
| Software Enable Mask. More... | |
| #define | XRGB_CTL_RUE_MASK 0x00000002 |
| Register Update Enable Mask. More... | |
| #define | XRGB_CTL_BPE_MASK 0x00000010 |
| Bypass Mask. More... | |
| #define | XRGB_CTL_TPE_MASK 0x00000020 |
| Test Pattern Mask. More... | |
| #define | XRGB_CTL_AUTORESET_MASK 0x40000000 |
| Software Reset - Auto-synchronize to SOF Mask. More... | |
| #define | XRGB_CTL_RESET_MASK 0x80000000 |
| Software Reset - Instantaneous Mask. More... | |
Slave Error Bit Masks | |
| #define | XRGB_ERR_EOL_EARLY_MASK 0x000000001 |
| Error: End of line Early Mask. More... | |
| #define | XRGB_ERR_EOL_LATE_MASK 0x000000002 |
| Error: End of line Late Mask. More... | |
| #define | XRGB_ERR_SOF_EARLY_MASK 0x000000004 |
| Error: Start of frame Early Mask. More... | |
| #define | XRGB_ERR_SOF_LATE_MASK 0x000000008 |
| Error: Start of frame Late Mask. More... | |
Interrupt Register Bit Masks | |
Interrupt Register bit definition for RGB2YCRCB core. It is applicable for STATUS and IRQ_ENABLE Registers. | |
| #define | XRGB_IXR_PROC_STARTED_MASK 0x00000001 |
| Process Started Mask. More... | |
| #define | XRGB_IXR_EOF_MASK 0x00000002 |
| End-Of-Frame Mask. More... | |
| #define | XRGB_IXR_SE_MASK 0x00010000 |
| Slave Error Mask. More... | |
| #define | XRGB_IXR_ALLINTR_MASK 0x00010003 |
| Interrupt All Error Mask (ORing (of All Interrupt Mask) More... | |
Version Register Bit Masks and Shifts | |
Version Register bit definition for RGB2YCRCB core. | |
| #define | XRGB_VER_REV_NUM_MASK 0x000000FF |
| Revision Number Mask. More... | |
| #define | XRGB_VER_PID_MASK 0x00000F00 |
| Patch ID Mask. More... | |
| #define | XRGB_VER_REV_MASK 0x0000F000 |
| Revision Mask. More... | |
| #define | XRGB_VER_MINOR_MASK 0x00FF0000 |
| Minor Mask. More... | |
| #define | XRGB_VER_MAJOR_MASK 0xFF000000 |
| Major Mask. More... | |
| #define | XRGB_VER_MAJOR_SHIFT 24 |
| Major Shift. More... | |
| #define | XRGB_VER_MINOR_SHIFT 16 |
| Minor Shift. More... | |
| #define | XGMA_VER_REV_SHIFT 12 |
| Revision Shift. More... | |
| #define | XRGB_VER_INTERNAL_SHIFT 8 |
| Internal Shift. More... | |
ActiveSize Register Bit Masks and Shift | |
| #define | XRGB_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF |
| The number of pixels in source image. More... | |
| #define | XRGB_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 |
| The number of lines in source image. More... | |
| #define | XRGB_ACTSIZE_NUM_LINE_SHIFT 16 |
| Shift for number of lines. More... | |
YMax Register Bit Mask | |
| #define | XRGB_YMAX_MASK 0x0000FFFF |
| Luma clipping value Mask. More... | |
YMin Register Bit Mask | |
| #define | XRGB_YMIN_MASK 0x0000FFFF |
| Luma clamping value Mask. More... | |
CBMax Register Bit Mask | |
| #define | XRGB_CBMAX_MASK 0x0000FFFF |
| Chroma Cb clipping value Mask. More... | |
CBMin Register Bit Mask | |
| #define | XRGB_CBMIN_MASK 0x0000FFFF |
| Chroma Cb clamping value mask. More... | |
CRMax Register Bit Mask | |
| #define | XRGB_CRMAX_MASK 0x0000FFFF |
| Chroma Cr clipping value Mask. More... | |
CRMin Register Bit Mask | |
| #define | XRGB_CRMIN_MASK 0x0000FFFF |
| Chroma Cr clamping value Mask. More... | |
YOffset Register Bit Mask | |
| #define | XRGB_YOFFSET_MASK 0x0001FFFF |
| Luma offset compensation value Mask. More... | |
CbOffset Register Bit Mask | |
| #define | XRGB_CBOFFSET_MASK 0x0001FFFF |
| Chroma(Cb) offset compensation value Mask. More... | |
CrOffset Register Bit Mask | |
| #define | XRGB_CROFFSET_MASK 0x0001FFFF |
| Chroma(Cr) offset compensation value Mask. More... | |
ACOEF, BCOEF, CCOEF, DCOEF Register Bit Mask | |
| #define | XRGB_COEFF_MASK 0x0001FFFF |
| Matrix Conversion Coefficient value mask. More... | |
General purpose Bit Mask and Shifts | |
| #define | XRGB_8_BIT_MASK 0x000000FF |
| 8-Bit mask More... | |
| #define | XRGB_16_BIT_MASK 0x0000FFFF |
| 16-Bit mask More... | |
| #define | XRGB_16_BIT_COEF_SHIFT 16 |
| 16-Bit Coefficient shift More... | |
Data widths in bits per color. | |
| #define | XRGB_DATA_WIDTH_8 8 |
| 8-bit Data Width More... | |
| #define | XRGB_DATA_WIDTH_10 10 |
| 10-bit Data Width More... | |
| #define | XRGB_DATA_WIDTH_12 12 |
| 12-bit Data Width More... | |
| #define | XRGB_DATA_WIDTH_16 16 |
| 16-bit Data Width More... | |
Backward Compatibility Macros | |
To support backward compatibility, following macro definitions are re-defined. | |
| #define | RGB_CONTROL XRGB_CONTROL_OFFSET |
| #define | RGB_STATUS XRGB_STATUS_OFFSET |
| #define | RGB_ERROR XRGB_ERROR_OFFSET |
| #define | RGB_IRQ_EN XRGB_IRQ_EN_OFFSET |
| #define | RGB_VERSION XRGB_VERSION_OFFSET |
| #define | RGB_SYSDEBUG0 XRGB_SYSDEBUG0_OFFSET |
| #define | RGB_SYSDEBUG1 XRGB_SYSDEBUG1_OFFSET |
| #define | RGB_SYSDEBUG2 XRGB_SYSDEBUG2_OFFSET |
| #define | RGB_ACTIVE_SIZE XRGB_ACTIVE_SIZE_OFFSET |
| #define | RGB_YMAX XRGB_YMAX_OFFSET |
| #define | RGB_YMIN XRGB_YMIN_OFFSET |
| #define | RGB_CBMAX XRGB_CBMAX_OFFSET |
| #define | RGB_CBMIN XRGB_CBMIN_OFFSET |
| #define | RGB_CRMAX XRGB_CRMAX_OFFSET |
| #define | RGB_CRMIN XRGB_CRMIN_OFFSET |
| #define | RGB_YOFFSET XRGB_YOFFSET_OFFSET |
| #define | RGB_CBOFFSET XRGB_CBOFFSET_OFFSET |
| #define | RGB_CROFFSET XRGB_CROFFSET_OFFSET |
| #define | RGB_ACOEF XRGB_ACOEF_OFFSET |
| #define | RGB_BCOEF XRGB_BCOEF_OFFSET |
| #define | RGB_CCOEF XRGB_CCOEF_OFFSET |
| #define | RGB_DCOEF XRGB_DCOEF_OFFSET |
| #define | RGB_CTL_EN_MASK XRGB_CTL_EN_MASK |
| #define | RGB_CTL_RUE_MASK XRGB_CTL_RUE_MASK |
| #define | RGB_RST_RESET XRGB_CTL_RESET_MASK |
| #define | RGB_RST_AUTORESET XRGB_CTL_AUTORESET_MASK |
| #define | RGB_In32 XRgb2YCrCb_In32 |
| #define | RGB_Out32 XRgb2YCrCb_Out32 |
Interrupt Registers | |
Interrupt status register generates a interrupt if the corresponding bits of interrupt enable register bits are set. | |
| #define | XRGB_ISR_OFFSET XRGB_STATUS_OFFSET |
| Interrupt Status Offset. More... | |
| #define | XRGB_IER_OFFSET XRGB_IRQ_EN_OFFSET |
| Interrupt Enable Offset. More... | |