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uartns550
Xilinx SDK Drivers API Documentation
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Macros | |
| #define | XUartNs550_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset)) |
| Read a UART register. More... | |
| #define | XUartNs550_WriteReg(BaseAddress, RegOffset, RegisterValue) Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) |
| Write to a UART register. More... | |
| #define | XUartNs550_GetLineStatusReg(BaseAddress) XUartNs550_ReadReg((BaseAddress), XUN_LSR_OFFSET) |
| Get the UART Line Status Register. More... | |
| #define | XUartNs550_GetLineControlReg(BaseAddress) XUartNs550_ReadReg((BaseAddress), XUN_LCR_OFFSET) |
| Get the UART Line Status Register. More... | |
| #define | XUartNs550_SetLineControlReg(BaseAddress, RegisterValue) XUartNs550_WriteReg((BaseAddress), XUN_LCR_OFFSET, (RegisterValue)) |
| Set the UART Line Status Register. More... | |
| #define | XUartNs550_EnableIntr(BaseAddress) |
| Enable the transmit and receive interrupts of the UART. More... | |
| #define | XUartNs550_DisableIntr(BaseAddress) |
| Disable the transmit and receive interrupts of the UART. More... | |
| #define | XUartNs550_IsReceiveData(BaseAddress) (XUartNs550_GetLineStatusReg(BaseAddress) & XUN_LSR_DATA_READY) |
| Determine if there is receive data in the receiver and/or FIFO. More... | |
| #define | XUartNs550_IsTransmitEmpty(BaseAddress) (XUartNs550_GetLineStatusReg(BaseAddress) & XUN_LSR_TX_BUFFER_EMPTY) |
| Determine if a byte of data can be sent with the transmitter. More... | |
Register Map | |
Register offsets for the 16450/16550 compatible UART device. | |
| #define | XUN_RBR_OFFSET (XUN_REG_OFFSET) |
| Receive buffer, read only. More... | |
| #define | XUN_THR_OFFSET (XUN_REG_OFFSET) |
| Transmit holding register. More... | |
| #define | XUN_IER_OFFSET (XUN_REG_OFFSET + 0x04) |
| Interrupt enable. More... | |
| #define | XUN_IIR_OFFSET (XUN_REG_OFFSET + 0x08) |
| Interrupt id, read only. More... | |
| #define | XUN_FCR_OFFSET (XUN_REG_OFFSET + 0x08) |
| Fifo control, write only. More... | |
| #define | XUN_LCR_OFFSET (XUN_REG_OFFSET + 0x0C) |
| Line Control Register. More... | |
| #define | XUN_MCR_OFFSET (XUN_REG_OFFSET + 0x10) |
| Modem Control Register. More... | |
| #define | XUN_LSR_OFFSET (XUN_REG_OFFSET + 0x14) |
| Line Status Register. More... | |
| #define | XUN_MSR_OFFSET (XUN_REG_OFFSET + 0x18) |
| Modem Status Register. More... | |
| #define | XUN_DRLS_OFFSET (XUN_REG_OFFSET + 0x00) |
| Divisor Register LSB. More... | |
| #define | XUN_DRLM_OFFSET (XUN_REG_OFFSET + 0x04) |
| Divisor Register MSB. More... | |
Interrupt Enable Register (IER) mask(s) | |
| #define | XUN_IER_MODEM_STATUS 0x00000008 |
| Modem status interrupt. More... | |
| #define | XUN_IER_RX_LINE 0x00000004 |
| Receive status interrupt. More... | |
| #define | XUN_IER_TX_EMPTY 0x00000002 |
| Transmitter empty interrupt. More... | |
| #define | XUN_IER_RX_DATA 0x00000001 |
| Receiver data available. More... | |
Interrupt ID Register (INT_ID) mask(s) | |
| #define | XUN_INT_ID_MASK 0x0000000F |
| Only the interrupt ID. More... | |
| #define | XUN_INT_ID_FIFOS_ENABLED 0x000000C0 |
| Only the FIFOs enable. More... | |
FIFO Control Register mask(s) | |
| #define | XUN_FIFO_RX_TRIG_MSB 0x00000080 |
| Trigger level MSB. More... | |
| #define | XUN_FIFO_RX_TRIG_LSB 0x00000040 |
| Trigger level LSB. More... | |
| #define | XUN_FIFO_TX_RESET 0x00000004 |
| Reset the transmit FIFO. More... | |
| #define | XUN_FIFO_RX_RESET 0x00000002 |
| Reset the receive FIFO. More... | |
| #define | XUN_FIFO_ENABLE 0x00000001 |
| Enable the FIFOs. More... | |
| #define | XUN_FIFO_RX_TRIGGER 0x000000C0 |
| Both trigger level bits. More... | |
Line Control Register(LCR) mask(s) | |
| #define | XUN_LCR_DLAB 0x00000080 |
| Divisor latch access. More... | |
| #define | XUN_LCR_SET_BREAK 0x00000040 |
| Cause a break condition. More... | |
| #define | XUN_LCR_STICK_PARITY 0x00000020 |
| Stick Parity. More... | |
| #define | XUN_LCR_EVEN_PARITY 0x00000010 |
| 1 = even, 0 = odd parity More... | |
| #define | XUN_LCR_ENABLE_PARITY 0x00000008 |
| 1 = Enable, 0 = Disable parity More... | |
| #define | XUN_LCR_2_STOP_BITS 0x00000004 |
| 1= 2 stop bits,0 = 1 stop bit More... | |
| #define | XUN_LCR_8_DATA_BITS 0x00000003 |
| 8 Data bits selection More... | |
| #define | XUN_LCR_7_DATA_BITS 0x00000002 |
| 7 Data bits selection More... | |
| #define | XUN_LCR_6_DATA_BITS 0x00000001 |
| 6 Data bits selection More... | |
| #define | XUN_LCR_LENGTH_MASK 0x00000003 |
| Both length bits mask. More... | |
| #define | XUN_LCR_PARITY_MASK 0x00000018 |
| Both parity bits mask. More... | |
Mode Control Register(MCR) mask(s) | |
| #define | XUN_MCR_LOOP 0x00000010 |
| Local loopback. More... | |
| #define | XUN_MCR_OUT_2 0x00000008 |
| General output 2 signal. More... | |
| #define | XUN_MCR_OUT_1 0x00000004 |
| General output 1 signal. More... | |
| #define | XUN_MCR_RTS 0x00000002 |
| RTS signal. More... | |
| #define | XUN_MCR_DTR 0x00000001 |
| DTR signal. More... | |
Line Status Register(LSR) mask(s) | |
| #define | XUN_LSR_RX_FIFO_ERROR 0x00000080 |
| An errored byte is in FIFO. More... | |
| #define | XUN_LSR_TX_EMPTY 0x00000040 |
| Transmitter is empty. More... | |
| #define | XUN_LSR_TX_BUFFER_EMPTY 0x00000020 |
| Transmit holding reg empty. More... | |
| #define | XUN_LSR_BREAK_INT 0x00000010 |
| Break detected interrupt. More... | |
| #define | XUN_LSR_FRAMING_ERROR 0x00000008 |
| Framing error on current byte. More... | |
| #define | XUN_LSR_PARITY_ERROR 0x00000004 |
| Parity error on current byte. More... | |
| #define | XUN_LSR_OVERRUN_ERROR 0x00000002 |
| Overrun error on receive FIFO. More... | |
| #define | XUN_LSR_DATA_READY 0x00000001 |
| Receive data ready. More... | |
| #define | XUN_LSR_ERROR_BREAK 0x0000001E |
| Errors except FIFO error and break detected. More... | |
Functions | |
| void | XUartNs550_SendByte (UINTPTR BaseAddress, u8 Data) |
| This function sends a data byte with the UART. More... | |
| u8 | XUartNs550_RecvByte (UINTPTR BaseAddress) |
| This function receives a byte from the UART. More... | |
| void | XUartNs550_SetBaud (UINTPTR BaseAddress, u32 InputClockHz, u32 BaudRate) |
| Set the baud rate for the UART. More... | |