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tft
Xilinx SDK Drivers API Documentation
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Macros | |
| #define | XTFT_CHAR_WIDTH 8 |
| Dimension Definitions. More... | |
| #define | XTFT_CHAR_HEIGHT 12 |
| Character height. More... | |
| #define | XTFT_DISPLAY_WIDTH 640 |
| Width of the screen. More... | |
| #define | XTFT_DISPLAY_HEIGHT 480 |
| Height of the screen. More... | |
| #define | XTFT_DISPLAY_BUFFER_WIDTH 1024 |
| Buffer width of a line. More... | |
| #define | XTFT_DCR_REG_SHIFT 2 |
| Reg Shift for DCR Access. More... | |
TFT Register offsets | |
The following definitions provide access to each of the registers of the TFT device. | |
| #define | XTFT_AR_OFFSET 0 |
| Address Reg (Video memory) Offset. More... | |
| #define | XTFT_CR_OFFSET 4 |
| Control Register Offset. More... | |
| #define | XTFT_IESR_OFFSET 8 |
| Interrupt Enable and Status Reg Offset. More... | |
| #define | XTFT_AR_LSB_OFFSET 0x10 |
| Address Reg LSB (Video memory) Offset. More... | |
| #define | XTFT_AR_MSB_OFFSET 0x14 |
| Address Reg MSB (Video memory) Offset. More... | |
TFT Control Register (CR) mask(s) | |
| #define | XTFT_CR_TDE_MASK 0x01 |
| TFT Display Enable Bit Mask. More... | |
| #define | XTFT_CR_DPS_MASK 0x02 |
| TFT Display Scan Control Bit Mask. More... | |
TFT Interrupt Enable and Status Register (IESR) mask(s) | |
| #define | XTFT_IESR_VADDRLATCH_STATUS_MASK 0x01 |
| TFT Video Address Latch Status Bit Mask. More... | |
| #define | XTFT_IESR_IE_MASK 0x08 |
| TFT Interrupt Enable Mask. More... | |