This design is targeted for xck26 board (part number: xck26-sfvc784-2lv-c)

Zynq UltraScale+ Design Summary

Device	xck26
SpeedGrade	-2lv
Part	xck26-sfvc784-2lv-c
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	slow	pullup	out	4
MIO 1	Quad SPI Flash	miso_mo1	cmos	slow	pullup	inout	4
MIO 2	Quad SPI Flash	mo2	cmos	slow	pullup	inout	4
MIO 3	Quad SPI Flash	mo3	cmos	slow	pullup	inout	4
MIO 4	Quad SPI Flash	mosi_mi0	cmos	slow	pullup	inout	4
MIO 5	Quad SPI Flash	n_ss_out	cmos	slow	pullup	out	4
MIO 6	SPI 1	sclk_out	cmos	slow	pullup	inout	4
MIO 7	GPIO0 MIO	gpio0[7]	cmos	slow	pullup	inout	4
MIO 8	GPIO0 MIO	gpio0[8]	cmos	slow	pullup	inout	4
MIO 9	SPI 1	n_ss_out[0]	cmos	slow	pullup	inout	4
MIO 10	SPI 1	miso	cmos	slow	pullup	inout	4
MIO 11	SPI 1	mosi	cmos	slow	pullup	inout	4
MIO 12	GPIO0 MIO	gpio0[12]	cmos	slow	pullup	inout	4
MIO 13	GPIO0 MIO	gpio0[13]	cmos	slow	pullup	inout	4
MIO 14	GPIO0 MIO	gpio0[14]	cmos	slow	pullup	inout	4
MIO 15	GPIO0 MIO	gpio0[15]	cmos	slow	pullup	inout	4
MIO 16	GPIO0 MIO	gpio0[16]	cmos	slow	pullup	inout	4
MIO 17	GPIO0 MIO	gpio0[17]	cmos	slow	pullup	inout	4
MIO 18	GPIO0 MIO	gpio0[18]	cmos	slow	pullup	inout	4
MIO 19	GPIO0 MIO	gpio0[19]	cmos	slow	pullup	inout	4
MIO 20	GPIO0 MIO	gpio0[20]	cmos	slow	pullup	inout	4
MIO 21	GPIO0 MIO	gpio0[21]	cmos	slow	pullup	inout	4
MIO 22	GPIO0 MIO	gpio0[22]	cmos	slow	pullup	inout	4
MIO 23	GPIO0 MIO	gpio0[23]	cmos	slow	pullup	inout	4
MIO 24	I2C 1	scl_out	cmos	slow	pullup	inout	4
MIO 25	I2C 1	sda_out	cmos	slow	pullup	inout	4
MIO 26	PMU GPI 0	gpi[0]	cmos	fast	pullup	in	12
MIO 27	DPAUX	dp_aux_data_out	cmos	slow	pullup	out	4
MIO 28	DPAUX	dp_hot_plug_detect	cmos	fast	pullup	in	12
MIO 29	DPAUX	dp_aux_data_oe	cmos	slow	pullup	out	4
MIO 30	DPAUX	dp_aux_data_in	cmos	fast	pullup	in	12
MIO 31	PMU GPI 5	gpi[5]	cmos	fast	pullup	in	12
MIO 32	GPIO1 MIO	gpio1[32]	cmos	slow	pullup	inout	4
MIO 33	GPIO1 MIO	gpio1[33]	cmos	slow	pullup	inout	4
MIO 34	GPIO1 MIO	gpio1[34]	cmos	slow	pullup	inout	4
MIO 35	PMU GPO 3	gpo[3]	cmos	slow	pullup	out	4
MIO 36	UART 1	txd	cmos	slow	pullup	out	4
MIO 37	UART 1	rxd	cmos	fast	pullup	in	12
MIO 38	Gem 1	rgmii_tx_clk	cmos	slow	pullup	out	4
MIO 39	Gem 1	rgmii_txd[0]	cmos	slow	pullup	out	4
MIO 40	Gem 1	rgmii_txd[1]	cmos	slow	pullup	out	4
MIO 41	Gem 1	rgmii_txd[2]	cmos	slow	pullup	out	4
MIO 42	Gem 1	rgmii_txd[3]	cmos	slow	pullup	out	4
MIO 43	Gem 1	rgmii_tx_ctl	cmos	slow	pullup	out	4
MIO 44	Gem 1	rgmii_rx_clk	cmos	fast	pullup	in	12
MIO 45	Gem 1	rgmii_rxd[0]	cmos	fast	disable	in	12
MIO 46	Gem 1	rgmii_rxd[1]	cmos	fast	pullup	in	12
MIO 47	Gem 1	rgmii_rxd[2]	cmos	fast	disable	in	12
MIO 48	Gem 1	rgmii_rxd[3]	cmos	fast	pullup	in	12
MIO 49	Gem 1	rgmii_rx_ctl	cmos	fast	disable	in	12
MIO 50	MDIO 1	gem1_mdc	cmos	slow	pullup	out	4
MIO 51	MDIO 1	gem1_mdio_out	cmos	slow	pullup	inout	4
MIO 52	USB 0	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 53	USB 0	ulpi_dir	cmos	fast	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	cmos	slow	pullup	inout	4
MIO 55	USB 0	ulpi_nxt	cmos	fast	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	cmos	slow	pullup	inout	4
MIO 57	USB 0	ulpi_tx_data[1]	cmos	slow	pullup	inout	4
MIO 58	USB 0	ulpi_stp	cmos	slow	pullup	out	4
MIO 59	USB 0	ulpi_tx_data[3]	cmos	slow	pullup	inout	4
MIO 60	USB 0	ulpi_tx_data[4]	cmos	slow	pullup	inout	4
MIO 61	USB 0	ulpi_tx_data[5]	cmos	slow	pullup	inout	4
MIO 62	USB 0	ulpi_tx_data[6]	cmos	slow	pullup	inout	4
MIO 63	USB 0	ulpi_tx_data[7]	cmos	slow	pullup	inout	4
MIO 64	USB 1	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 65	USB 1	ulpi_dir	cmos	fast	pullup	in	12
MIO 66	USB 1	ulpi_tx_data[2]	cmos	slow	pullup	inout	4
MIO 67	USB 1	ulpi_nxt	cmos	fast	pullup	in	12
MIO 68	USB 1	ulpi_tx_data[0]	cmos	slow	pullup	inout	4
MIO 69	USB 1	ulpi_tx_data[1]	cmos	slow	pullup	inout	4
MIO 70	USB 1	ulpi_stp	cmos	slow	pullup	out	4
MIO 71	USB 1	ulpi_tx_data[3]	cmos	slow	pullup	inout	4
MIO 72	USB 1	ulpi_tx_data[4]	cmos	slow	pullup	inout	4
MIO 73	USB 1	ulpi_tx_data[5]	cmos	slow	pullup	inout	4
MIO 74	USB 1	ulpi_tx_data[6]	cmos	slow	pullup	inout	4
MIO 75	USB 1	ulpi_tx_data[7]	cmos	slow	pullup	inout	4
MIO 76	USB0 Reset	reset	cmos	slow	pullup	out	4
MIO 77	USB1 Reset	reset	cmos	slow	pullup	out	4

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2666.640
DPLL	PSS_REF_CLK	2133.312
VPLL	PSS_REF_CLK	2999.970
RPLL	PSS_REF_CLK	2133.312
IOPLL	PSS_REF_CLK	1999.980

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM0 freq (MHz)	125	IOPLL	124.998749
GEM1 freq (MHz)	125	IOPLL	124.998749
USB0 freq (MHz)	250	IOPLL	249.997498
USB1 freq (MHz)	250	IOPLL	249.997498
QSPI freq (MHz)	125	IOPLL	124.998749
UART1 freq (MHz)	100	IOPLL	99.999001
I2C1 freq (MHz)	100	IOPLL	99.999001
SPI1 freq (MHz)	200	IOPLL	199.998001
CPU_R5 freq (MHz)	533.333	RPLL	533.328003
IOU_SWITCH freq (MHz)	250	IOPLL	249.997498
LPD_SWITCH freq (MHz)	500	IOPLL	499.994995
LPD_LSBUS freq (MHz)	100	IOPLL	99.999001
GEM_TSU freq (MHz)	250	IOPLL	249.997498
TIMESTAMP freq (MHz)	100	IOPLL	99.999001
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	19.999800
PCAP freq (MHz)	200	IOPLL	199.998001
DBG_LPD freq (MHz)	250	IOPLL	249.997498
ADMA freq (MHz)	500	IOPLL	499.994995
PL0 freq (MHz)	100	IOPLL	99.999001
PL1 freq (MHz)	100	IOPLL	99.999001
AMS freq (MHz)	50	IOPLL	49.999500
ACPU freq (MHz)	1333.333	APLL	1333.333008
DBG FPD freq (MHz)	250	IOPLL	249.997498
DP VIDEO freq (MHz)	300	VPLL	299.997009
DP AUDIO freq (MHz)	25	RPLL	24.242182
DP STC freq (MHz)	27	RPLL	26.666401
DDR_CTRL freq MHz)	600.000	DPLL	533.328003
GPU freq (MHz)	600	IOPLL	499.994995
GDMA freq (MHz)	600	DPLL	533.328003
DPDMA freq (MHz)	600	APLL	444.444336
TOPSW_MAIN freq (MHz)	533.33	DPLL	533.328003
TOPSW_LSBUS freq (MHz)	100	IOPLL	99.999001
DBG TSTMP freq (MHz)	250	IOPLL	249.997498

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1200	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR4_2400R	Speed Bin
CL	16	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	14	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	16	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	16	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	47.06	Row cycle time (ns)
T RAS MIN	33	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	16 Bits	Width of individual DRAM components
DEVICE CAPACITY	8192 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	1	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	16	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0xFFFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
Gem0	GT Lane0	Ref Clk0	125
DP	GT Lane1	Ref Clk1	27
USB0	GT Lane2	Ref Clk2	26
USB1	GT Lane3	Ref Clk3	26