• Zynq UltraScale+ PS Summary Viewer
    • Zynq UltraScale+ Summary Report
    User Configurations
    MIO Configurations
    CLK Configurations
    DDR Configurations
    GT Configurations
    This design is targeted for xczu4eg board (part number: xczu4eg-sfvc784-2-i)

    Zynq UltraScale+ Design Summary

    Device xczu4eg
    SpeedGrade -2
    Part xczu4eg-sfvc784-2-i
    Description Zynq UltraScale+ PS Configuration Report
    Vendor Xilinx

    MIO Table View

    MIO Pin Peripheral Signal IO Type Speed Pullup Direction Drive Strength(mA)
    MIO 0 Quad SPI Flash sclk_out cmos fast pullup out 12
    MIO 1 Quad SPI Flash miso_mo1 cmos fast pullup inout 12
    MIO 2 Quad SPI Flash mo2 cmos fast pullup inout 12
    MIO 3 Quad SPI Flash mo3 cmos fast pullup inout 12
    MIO 4 Quad SPI Flash mosi_mi0 cmos fast pullup inout 12
    MIO 5 Quad SPI Flash n_ss_out cmos fast pullup out 12
    MIO 6 GPIO0 MIO gpio0[6] cmos fast pullup inout 12
    MIO 7 GPIO0 MIO gpio0[7] cmos fast pullup inout 12
    MIO 8 GPIO0 MIO gpio0[8] cmos fast pullup inout 12
    MIO 9 GPIO0 MIO gpio0[9] cmos fast pullup inout 12
    MIO 10 GPIO0 MIO gpio0[10] cmos fast pullup inout 12
    MIO 11 GPIO0 MIO gpio0[11] cmos fast pullup inout 12
    MIO 12 GPIO0 MIO gpio0[12] cmos fast pullup inout 12
    MIO 13 SD 0 sdio0_data_out[0] cmos fast pullup inout 12
    MIO 14 SD 0 sdio0_data_out[1] cmos fast pullup inout 12
    MIO 15 SD 0 sdio0_data_out[2] cmos fast pullup inout 12
    MIO 16 SD 0 sdio0_data_out[3] cmos fast pullup inout 12
    MIO 17 SD 0 sdio0_data_out[4] cmos fast pullup inout 12
    MIO 18 SD 0 sdio0_data_out[5] cmos fast pullup inout 12
    MIO 19 SD 0 sdio0_data_out[6] cmos fast pullup inout 12
    MIO 20 SD 0 sdio0_data_out[7] cmos fast pullup inout 12
    MIO 21 SD 0 sdio0_cmd_out cmos fast pullup inout 12
    MIO 22 SD 0 sdio0_clk_out cmos fast pullup out 12
    MIO 23 SD 0 sdio0_bus_pow cmos fast pullup out 12
    MIO 24 I2C 1 scl_out cmos fast pullup inout 12
    MIO 25 I2C 1 sda_out cmos fast pullup inout 12
    MIO 26 UART 0 rxd cmos fast pullup in 12
    MIO 27 UART 0 txd cmos fast pullup out 12
    MIO 28 cmos fast pullup 12
    MIO 29 cmos fast pullup 12
    MIO 30 cmos fast pullup 12
    MIO 31 cmos fast pullup 12
    MIO 32 cmos fast pullup 12
    MIO 33 cmos fast pullup 12
    MIO 34 I2C 0 scl_out cmos fast pullup inout 12
    MIO 35 I2C 0 sda_out cmos fast pullup inout 12
    MIO 36 UART 1 txd cmos fast pullup out 12
    MIO 37 UART 1 rxd cmos fast pullup in 12
    MIO 38 Gem 1 rgmii_tx_clk cmos fast pullup out 12
    MIO 39 Gem 1 rgmii_txd[0] cmos fast pullup out 12
    MIO 40 Gem 1 rgmii_txd[1] cmos fast pullup out 12
    MIO 41 Gem 1 rgmii_txd[2] cmos fast pullup out 12
    MIO 42 Gem 1 rgmii_txd[3] cmos fast pullup out 12
    MIO 43 Gem 1 rgmii_tx_ctl cmos fast pullup out 12
    MIO 44 Gem 1 rgmii_rx_clk cmos fast pullup in 12
    MIO 45 Gem 1 rgmii_rxd[0] cmos fast disable in 12
    MIO 46 Gem 1 rgmii_rxd[1] cmos fast disable in 12
    MIO 47 Gem 1 rgmii_rxd[2] cmos fast disable in 12
    MIO 48 Gem 1 rgmii_rxd[3] cmos fast disable in 12
    MIO 49 Gem 1 rgmii_rx_ctl cmos fast disable in 12
    MIO 50 MDIO 1 gem1_mdc cmos fast pullup out 12
    MIO 51 MDIO 1 gem1_mdio_out cmos fast pullup inout 12
    MIO 52 GPIO2 MIO gpio2[52] cmos fast pullup inout 12
    MIO 53 GPIO2 MIO gpio2[53] cmos fast pullup inout 12
    MIO 54 GPIO2 MIO gpio2[54] cmos fast pullup inout 12
    MIO 55 GPIO2 MIO gpio2[55] cmos fast pullup inout 12
    MIO 56 GPIO2 MIO gpio2[56] cmos fast pullup inout 12
    MIO 57 GPIO2 MIO gpio2[57] cmos fast pullup inout 12
    MIO 58 GPIO2 MIO gpio2[58] cmos fast pullup inout 12
    MIO 59 GPIO2 MIO gpio2[59] cmos fast pullup inout 12
    MIO 60 GPIO2 MIO gpio2[60] cmos fast pullup inout 12
    MIO 61 GPIO2 MIO gpio2[61] cmos fast pullup inout 12
    MIO 62 GPIO2 MIO gpio2[62] cmos fast pullup inout 12
    MIO 63 GPIO2 MIO gpio2[63] cmos fast pullup inout 12
    MIO 64 GPIO2 MIO gpio2[64] cmos fast pullup inout 12
    MIO 65 GPIO2 MIO gpio2[65] cmos fast pullup inout 12
    MIO 66 GPIO2 MIO gpio2[66] cmos fast pullup inout 12
    MIO 67 GPIO2 MIO gpio2[67] cmos fast pullup inout 12
    MIO 68 GPIO2 MIO gpio2[68] cmos fast pullup inout 12
    MIO 69 GPIO2 MIO gpio2[69] cmos fast pullup inout 12
    MIO 70 GPIO2 MIO gpio2[70] cmos fast pullup inout 12
    MIO 71 GPIO2 MIO gpio2[71] cmos fast pullup inout 12
    MIO 72 GPIO2 MIO gpio2[72] cmos fast pullup inout 12
    MIO 73 GPIO2 MIO gpio2[73] cmos fast pullup inout 12
    MIO 74 GPIO2 MIO gpio2[74] cmos fast pullup inout 12
    MIO 75 GPIO2 MIO gpio2[75] cmos fast pullup inout 12
    MIO 76 GPIO2 MIO gpio2[76] cmos fast pullup inout 12
    MIO 77 GPIO2 MIO gpio2[77] cmos fast pullup inout 12

    PS Clocks information

    PSS REF CLK : 33.333
    Name Source Input Frequency (MHz)
    APLL PSS_REF_CLK 2666.640
    DPLL PSS_REF_CLK 2399.976
    VPLL PSS_REF_CLK 2133.312
    RPLL PSS_REF_CLK 2133.312
    IOPLL PSS_REF_CLK 2999.970

    Peripheral Requested Frequency (MHz) Source Actual Frequency (MHz)
    GEM1 freq (MHz) 125 IOPLL 124.998749
    QSPI freq (MHz) 300 IOPLL 299.997009
    SDIO0 freq (MHz) 200 RPLL 177.776001
    UART0 freq (MHz) 100 IOPLL 99.999001
    UART1 freq (MHz) 100 IOPLL 99.999001
    I2C0 freq (MHz) 100 IOPLL 99.999001
    I2C1 freq (MHz) 100 IOPLL 99.999001
    CPU_R5 freq (MHz) 533.333 RPLL 533.328003
    IOU_SWITCH freq (MHz) 267 RPLL 266.664001
    LPD_SWITCH freq (MHz) 533.333 RPLL 533.328003
    LPD_LSBUS freq (MHz) 100 IOPLL 99.999001
    GEM_TSU freq (MHz) 250 IOPLL 249.997498
    TIMESTAMP freq (MHz) 100 PSS_REF_CLK 33.333000
    PCAP freq (MHz) 200 IOPLL 187.498123
    DBG_LPD freq (MHz) 250 IOPLL 249.997498
    ADMA freq (MHz) 533.333 RPLL 533.328003
    PL0 freq (MHz) 100 RPLL 96.968727
    AMS freq (MHz) 50 IOPLL 49.999500
    ACPU freq (MHz) 1333.333 APLL 1333.320068
    DBG FPD freq (MHz) 250 IOPLL 249.997498
    DDR_CTRL freq MHz) 533.500 DPLL 399.996002
    GPU freq (MHz) 600 DPLL 599.994019
    GDMA freq (MHz) 600 DPLL 599.994019
    DPDMA freq (MHz) 600 DPLL 599.994019
    TOPSW_MAIN freq (MHz) 533.333 VPLL 533.328003
    TOPSW_LSBUS freq (MHz) 100 IOPLL 99.999001
    DBG TSTMP freq (MHz) 250 IOPLL 249.997498

    DDR Memory information

    Parameter name Value Description
    ENABLE 1 Enable the PS DDR Controller
    DDR Interface freq (MHz) 1067 --
    MEMORY TYPE LPDDR 4 Type of memory interface
    DM DBI Components
    BUS WIDTH 32 Bit Data width of DDR interface, not including ECC data width
    ECC Disabled Enables error correction code support
    SPEED BIN LPDDR4_2133 Speed Bin
    CL NA Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
    CWL NA CAS write latency setting in memory clock cycles
    DDR AL 0 Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
    T RCD 20 tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
    T RP 23 Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
    T RC 63 Row cycle time (ns)
    T RAS MIN 42 Minimum number of memory clock cycles required between an Active and Precharge command
    T FAW 40 Determines the number of activates that can be performed within a certain window of time
    DRAM WIDTH 32 Bits Width of individual DRAM components
    DEVICE CAPACITY 16384 MBits Storage capacity of individual DRAM components
    BG ADDR COUNT NA Number of bank group address pins
    RANK ADDR COUNT 0 Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
    BANK ADDR COUNT 3 Number of bank address pins
    ROW ADDR COUNT 16 Number of row address pins
    COL ADDR COUNT 10 Number of column address bits
    C_DDR_RAM_HIGHADDR 0x7FFFFFFF --

    GT lanes information

    Protocol GT lane# Ref Clk Sel Ref freq (MHz)