{ "License" : "Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: MIT", "VE-P-A1225-00" : { "FEATURE" : { "List" : ["eeprom", "bootmode", "clock", "temp", "gpio"] }, "BOOTMODES" : { "Mode_Lines" : ["SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3"], "Modes" : { "JTAG" : "0x0", "QSPI_24" : "0x1", "QSPI_32" : "0x2", "SD_LS_SE11" : "0x3", "SD_2.0" : "0x5", "eMMC" : "0x6", "USB" : "0x7", "OSPI" : "0x8", "SMAP" : "0xa", "UFS" : "0xb", "DFT" : "0xd", "SD_LS_SE10" : "0xe" } }, "JTAGSELECTS" : { "Select_Lines" : ["SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1"], "Selects" : { "SC" : "0x0", "FTDI" : "0x1", "EXT" : "0x2" } }, "CLOCK" : { "QSFP_0_REFCLK" : { "Name" : "QSFP_0_REFCLK", "Type" : "ProXO-XP", "Sysfs_Path" : "/sys/devices/platform/sys-clk-0/set_rate", "Default_Freq" : 40.0, "Upper_Freq" : 2100.0, "Lower_Freq" : 15.0, "I2C_Bus" : "/dev/i2c-1", "I2C_Address" : "0x72" }, "CCIO_OSC_CLK" : { "Name" : "CCIO_OSC_CLK", "Type" : "ProXO-XP", "Sysfs_Path" : "/sys/devices/platform/sys-clk-1/set_rate", "Default_Freq" : 200.0, "Upper_Freq" : 2100.0, "Lower_Freq" : 15.0, "I2C_Bus" : "/dev/i2c-1", "I2C_Address" : "0x62" }, "XPN7_REF_CLK" : { "Name" : "XPN7_REF_CLK", "Type" : "ProXO-XP", "Sysfs_Path" : "/sys/devices/platform/sys-clk-2/set_rate", "Default_Freq" : 40.0, "Upper_Freq" : 2100.0, "Lower_Freq" : 15.0, "I2C_Bus" : "/dev/i2c-1", "I2C_Address" : "0x61" } }, "Temperature" : { "Name" : "Versal-APEX", "Sensor" : "versal-isa-0000" }, "GPIO_Group" : { "SW10" : { "Name" : "SW10", "Type" : "RW", "GPIO_Lines" : ["SYSCTLR_VERSAL_MODE3", "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE1", "SYSCTLR_VERSAL_MODE0"] }, "SW10 Readback" : { "Name" : "SW10 Readback", "Type" : "RO", "GPIO_Lines" : ["SYSCTLR_VERSAL_MODE3_READBACK", "SYSCTLR_VERSAL_MODE2_READBACK", "SYSCTLR_VERSAL_MODE1_READBACK", "SYSCTLR_VERSAL_MODE0_READBACK"] }, "SW3" : { "Name" : "SW3", "Type" : "RW", "GPIO_Lines" : ["SYSCTLR_JTAG_S1", "SYSCTLR_JTAG_S0"] }, "UFS Clock" : { "Name" : "UFS_CLK_SEL", "Type" : "RW", "GPIO_Lines" : ["UFS_CLK_SEL2", "UFS_CLK_SEL1", "UFS_CLK_SEL0"] } }, "GPIO" : { "UART_MUXSEL0" : "SCM_UART_MUX_SEL0", "UART_MUXSEL1" : "SCM_UART_MUX_SEL1", "SYSCTLR_JTAG_S0" : "SYSCTLR_JTAG_MUX_SEL0", "SYSCTLR_JTAG_S1" : "SYSCTLR_JTAG_MUX_SEL1", "SYSCTLR_VERSAL_MODE0" : "SYSCTLR_DUT_MODE0", "SYSCTLR_VERSAL_MODE1" : "SYSCTLR_DUT_MODE1", "SYSCTLR_VERSAL_MODE2" : "SYSCTLR_DUT_MODE2", "SYSCTLR_VERSAL_MODE3" : "SYSCTLR_DUT_MODE3", "SYSCTLR_VERSAL_MODE0_READBACK_RO" : "SYSCTLR_DUT_MODE_RDBK_0", "SYSCTLR_VERSAL_MODE1_READBACK_RO" : "SYSCTLR_DUT_MODE_RDBK_1", "SYSCTLR_VERSAL_MODE2_READBACK_RO" : "SYSCTLR_DUT_MODE_RDBK_2", "SYSCTLR_VERSAL_MODE3_READBACK_RO" : "SYSCTLR_DUT_MODE_RDBK_3", "VERSAL_DONE_RO" : "SYSCTLR_DUT_DONE", "VERSAL_ERROR_OUT_LS_RO" : "SYSCTLR_DUT_ERR_OUT", "SYSCTLR_POR_B_LS" : "SYSCTLR_DUT_POR_B", "SYSCTLR_VERSAL_POR_B_READBACK_RO" : "SYSCTLR_DUT_POR_B_RDBK", "BB_SW_ON_RO" : "SYSCTLR_BB_SW_ON_STATUS", "BB_PWR_DIS_B" : "SYSCTLR_BB_PWR_DIS_B", "DUT_PWR_DIS_B" : "SYSCTLR_DUT_PWR_DIS_B", "BB_SEQ_DIS_B" : "SYSCTLR_BB_SEQ_DIS_B", "BB_PGOOD_RO" : "SYSCTLR_BB_PGOOD", "DUT_GPIO0" : "SYSCTLR_GPIO0_LS", "DUT_GPIO1" : "SYSCTLR_GPIO1_LS", "UFS_CLK_SEL0" : "UFS_CLK_SEL_0", "UFS_CLK_SEL1" : "UFS_CLK_SEL_1", "UFS_CLK_SEL2" : "UFS_CLK_SEL_2", "FMCP1_FMC_PRSNT_M2C_B_RO" : "FMCP1_FMC_PRSNT_M2C_B", "UTIL_1V8_EN_OD" : "SYSCTLR_UTIL_1V8_EN", "DC_PRSNT_RO" : "DC_PRSNT", "DC_SYS_CTRL0" : "DC_SYS_CTRL0", "DC_SYS_CTRL1" : "DC_SYS_CTRL1", "DC_SYS_CTRL2" : "DC_SYS_CTRL2", "DC_SYS_CTRL3" : "DC_SYS_CTRL3", "DC_SYS_CTRL4" : "DC_SYS_CTRL4", "DC_SYS_CTRL5_POR_B_SW2" : "DC_SYS_CTRL5_POR_B_SW2", "ATX_PWR_OK_RO" : "ATX_PWR_OK", "UTIL_1V8_PG_RO" : "UTIL_1V8_PGOOD", "TI_CABLE_B" : "TI_CABLE_B", "UFS_VCCQ_1V2_EN_OD" : "SYSCTLR_UFS_VCCQ_1V2_EN", "UFS_VCC_EN_OD" : "SYSCTLR_UFS_VCC_EN", "LP5_VDD2_1V05_EN_OD" : "SYSCTLR_LP5_VDD2_1V05_EN", "LP5_VDDQ_0V5_EN_OD" : "SYSCTLR_LP5_VDDQ_0V5_EN", "VCCO_500_EN_OD" : "SYSCTLR_VCCO_500_EN", "VCCO_501_EN_OD" : "SYSCTLR_VCCO_501_EN", "VCCO_502_EN_OD" : "SYSCTLR_VCCO_502_EN", "VCCO_503_EN_OD" : "SYSCTLR_VCCO_503_EN", "VCCO_504_EN_OD" : "SYSCTLR_VCCO_504_EN", "VCCO_505_EN_OD" : "SYSCTLR_VCCO_505_EN", "VCC_MIPI_507_EN_OD" : "SYSCTLR_VCC_MIPI_507_EN", "VCCIO_MIPI_507_EN_OD" : "SYSCTLR_VCCIO_MIPI_507_EN", "VCC_LPD_EN_OD" : "SYSCTLR_VCC_LPD_EN", "VCCAUX_LPD_EN_OD" : "SYSCTLR_VCCAUX_LPD_EN", "VCC_FPD_EN_OD" : "SYSCTLR_VCC_FPD_EN", "VCCAUX_EN_OD" : "SYSCTLR_VCCAUX_EN", "VCC_SOC_EN_OD" : "SYSCTLR_VCC_SOC_EN", "VCCINT_EN_OD" : "SYSCTLR_VCCINT_EN", "VCC_RAM_EN_OD" : "SYSCTLR_VCC_RAM_EN", "VCCO_700_705_EN_OD" : "SYSCTLR_VCCO_700-705_EN", "VCCO_706_707_EN_OD" : "SYSCTLR_VCCO_706-707_EN", "VCCO_708_709_EN_OD" : "SYSCTLR_VCCO_708-709_EN", "VCCO_201_202_EN_OD" : "SYSCTLR_VCCO_201-202_EN", "VCCO_203_EN_OD" : "SYSCTLR_VCCO_203_EN", "VCC_SEIO_104_EN_OD" : "SYSCTLR_VCC_SEIO_104_EN", "VCCIO_SEIO_104_EN_OD" : "SYSCTLR_VCCIO_SEIO_104_EN", "VCC_SVIP_204_EN_OD" : "SYSCTLR_VCC_SVIP_204_EN", "VCCIO_SVIP_204_EN_OD" : "SYSCTLR_VCCIO_SVIP_204_EN", "UFS_VCCQ_1V2_PG_RO" : "UFS_VCCQ_1V2_PGOOD", "UFS_VCC_PG_RO" : "UFS_VCC_PGOOD", "LP5_VDD2_1V05_PG_RO" : "LP5_VDD2_1V05_PGOOD", "LP5_VDDQ_0V5_PG_RO" : "LP5_VDDQ_0V5_PGOOD", "VCCO_500_PG_RO" : "VCCO_500_PGOOD", "VCCO_501_PG_RO" : "VCCO_501_PGOOD", "VCCO_502_PG_RO" : "VCCO_502_PGOOD", "VCCO_503_PG_RO" : "VCCO_503_PGOOD", "VCCO_504_PG_RO" : "VCCO_504_PGOOD", "VCCO_505_PG_RO" : "VCCO_505_PGOOD", "VCC_MIPI_507_PG_RO" : "VCC_MIPI_507_PGOOD", "VCCIO_MIPI_507_PG_RO" : "VCCIO_MIPI_507_PGOOD", "VCC_LPD_PG_RO" : "VCC_LPD_PGOOD", "VCCAUX_LPD_PG_RO" : "VCCAUX_LPD_PGOOD", "VCC_FPD_PG_RO" : "VCC_FPD_PGOOD", "VCCAUX_PG_RO" : "VCCAUX_PGOOD", "VCC_SOC_PG_RO" : "VCC_SOC_PGOOD", "VCCINT_PG_RO" : "VCCINT_PGOOD", "VCC_RAM_PG_RO" : "VCC_RAM_PGOOD", "VCCO_700_705_PG_RO" : "VCCO_700-705_PGOOD", "VCCO_706_707_PG_RO" : "VCCO_706-707_PGOOD", "VCCO_708_709_PG_RO" : "VCCO_708-709_PGOOD", "VCCO_201_202_PG_RO" : "VCCO_201-202_PGOOD", "VCCO_203_PG_RO" : "VCCO_203_PGOOD", "VCC_SEIO_104_PG_RO" : "VCC_SEIO_104_PGOOD", "VCCIO_SEIO_104_PG_RO" : "VCCIO_SEIO_104_PGOOD", "VCC_SVIP_204_PG_RO" : "VCC_SVIP_204_PGOOD", "VCCIO_SVIP_204_PG_RO" : "VCCIO_SVIP_204_PGOOD", "SVIP_MIO_PAD00" : "SVIP_MIO_PAD00", "SVIP_MIO_PAD01" : "SVIP_MIO_PAD01", "SVIP_MIO_PAD02" : "SVIP_MIO_PAD02", "SVIP_MIO_PAD03" : "SVIP_MIO_PAD03", "SVIP_MIO_PAD04" : "SVIP_MIO_PAD04", "SVIP_MIO_PAD05" : "SVIP_MIO_PAD05", "SVIP_MIO_PAD06" : "SVIP_MIO_PAD06", "SVIP_MIO_PAD07" : "SVIP_MIO_PAD07", "SVIP_MIO_PAD08" : "SVIP_MIO_PAD08", "SVIP_MIO_PAD09" : "SVIP_MIO_PAD09", "SVIP_MIO_PAD10" : "SVIP_MIO_PAD10", "SVIP_MIO_PAD11" : "SVIP_MIO_PAD11", "SVIP_MIO_PAD12" : "SVIP_MIO_PAD12", "SVIP_MIO_PAD13" : "SVIP_MIO_PAD13", "SVIP_MIO_PAD14" : "SVIP_MIO_PAD14", "SVIP_MIO_PAD15" : "SVIP_MIO_PAD15", "SVIP_MIO_PAD16" : "SVIP_MIO_PAD16", "SVIP_MIO_PAD17" : "SVIP_MIO_PAD17", "SVIP_MIO_PAD18" : "SVIP_MIO_PAD18", "SVIP_MIO_PAD19" : "SVIP_MIO_PAD19", "SVIP_MIO_PAD20" : "SVIP_MIO_PAD20", "SVIP_MIO_PAD21" : "SVIP_MIO_PAD21", "SVIP_MIO_PAD22" : "SVIP_MIO_PAD22", "SVIP_MIO_PAD23" : "SVIP_MIO_PAD23", "SVIP_MIO_PAD24" : "SVIP_MIO_PAD24", "SVIP_MIO_PAD25" : "SVIP_MIO_PAD25", "SVIP_MIO_PAD26" : "SVIP_MIO_PAD26", "SVIP_MIO_PAD33" : "SVIP_MIO_PAD33", "SVIP_MIO_PAD34" : "SVIP_MIO_PAD34", "SVIP_MIO_PAD35" : "SVIP_MIO_PAD35", "SVIP_MIO_PAD36" : "SVIP_MIO_PAD36", "SVIP_MIO_PAD37" : "SVIP_MIO_PAD37", "SVIP_MIO_PAD38" : "SVIP_MIO_PAD38", "SVIP_MIO_PAD39" : "SVIP_MIO_PAD39", "SVIP_MIO_PAD40" : "SVIP_MIO_PAD40", "SVIP_MIO_PAD41" : "SVIP_MIO_PAD41", "SVIP_MIO_PAD42" : "SVIP_MIO_PAD42", "SVIP_MIO_PAD43" : "SVIP_MIO_PAD43", "SVIP_MIO_PAD52" : "SVIP_MIO_PAD52", "SVIP_MIO_PAD53" : "SVIP_MIO_PAD53", "SVIP_MIO_PAD54" : "SVIP_MIO_PAD54", "SVIP_MIO_PAD55" : "SVIP_MIO_PAD55", "SVIP_MIO_PAD56" : "SVIP_MIO_PAD56", "SVIP_MIO_PAD57" : "SVIP_MIO_PAD57", "SVIP_MIO_PAD58" : "SVIP_MIO_PAD58", "SVIP_MIO_PAD59" : "SVIP_MIO_PAD59", "SVIP_MIO_PAD60" : "SVIP_MIO_PAD60", "SVIP_MIO_PAD61" : "SVIP_MIO_PAD61", "SVIP_MIO_PAD62" : "SVIP_MIO_PAD62", "SVIP_MIO_PAD63" : "SVIP_MIO_PAD63", "SVIP_MIO_PAD64" : "SVIP_MIO_PAD64", "SVIP_MIO_PAD65" : "SVIP_MIO_PAD65", "SVIP_MIO_PAD66" : "SVIP_MIO_PAD66", "SVIP_MIO_PAD67" : "SVIP_MIO_PAD67", "SVIP_MIO_PAD68" : "SVIP_MIO_PAD68", "SVIP_MIO_PAD69" : "SVIP_MIO_PAD69" } } }