{ "License" : "Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: MIT", "VRK160" : { "FEATURE" : { "List" : ["eeprom", "bootmode", "clock", "temp", "gpio", "FMC", "BIT"] }, "BOOTMODES" : { "Mode_Lines" : ["SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3"], "Modes" : { "JTAG" : "0x0", "OSPI" : "0x8", "SD" : "0xe" } }, "JTAGSELECTS" : { "Select_Lines" : ["SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1"], "Selects" : { "SC" : "0x0", "FTDI" : "0x1", "EXT" : "0x2" } }, "CLOCK" : { "SiT95314_1_CLK" : { "Name" : "SiT95314_1_CLK", "Type" : "SIT95314", "Vendor_Managed" : 1, "Default_Design" : "VRK160_SiT95314_1", "I2C_Bus" : "/dev/i2c-8", "I2C_Address" : "0x69", "FPGA_Counter_Reg" : ["0x0", "0x0", "0xA4010000", "0xA40A0000"] }, "SiT95314_2_CLK" : { "Name" : "SiT95314_2_CLK", "Type" : "SIT95314", "Vendor_Managed" : 1, "Default_Design" : "VRK160_SiT95314_2", "I2C_Bus" : "/dev/i2c-7", "I2C_Address" : "0x69", "FPGA_Counter_Reg" : ["0xA4080000", "0x0", "0xA4090000", "0xA4050000"] } }, "Temperature" : { "Name" : "Versal", "Sensor" : "versal-isa-0000" }, "GPIO_Group" : { "SW3" : { "Name" : "SW3", "Type" : "RW", "GPIO_Lines" : ["SYSCTLR_VERSAL_MODE3", "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE1", "SYSCTLR_VERSAL_MODE0"] }, "SW3 Readback" : { "Name" : "SW3 Readback", "Type" : "RO", "GPIO_Lines" : ["SYSCTLR_VERSAL_MODE3_READBACK", "SYSCTLR_VERSAL_MODE2_READBACK", "SYSCTLR_VERSAL_MODE1_READBACK", "SYSCTLR_VERSAL_MODE0_READBACK"] }, "SW8" : { "Name" : "SW8", "Type" : "RW", "GPIO_Lines" : ["SYSCTLR_JTAG_S1", "SYSCTLR_JTAG_S0"] } }, "GPIO" : { "SFP_04_TX_FAULT" : "SFP_04_TX_FAULT", "SFP_04_RX_LOS" : "SFP_04_RX_LOS", "SFP_04_MOD_ABS" : "SFP_04_MOD_ABS", "SFP_04_TX_DISABLE" : "SFP_04_TX_DISABLE", "SFP_04_RS0" : "SFP_04_RS0", "SFP_04_RS1" : "SFP_04_RS1", "FMCP1_FMC_PRSNT_M2C_B" : "FMCP1_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B" : "FMCP1_FMCP_PRSNT_M2C_B", "PMBUS4_INA_ALERT" : "PMBUS4_INA_ALERT", "PMBUS3_INA_ALERT" : "PMBUS3_INA_ALERT", "PMBUS2_INA_ALERT" : "PMBUS2_INA_ALERT", "PMBUS1_INA_ALERT" : "PMBUS1_INA_ALERT", "PMBUS1_NIRQ" : "PMBUS_SEQ_NIRQ", "PMBUS1_ALERT" : "PMBUS1_ALERT", "QSFP1_MODSELL" : "QSFP1_MODSELL", "QSFP1_RESETL" : "QSFP1_RESETL", "QSFP1_MODPRSL" : "QSFP1_MODPRSL", "QSFP1_INTL" : "QSFP1_INTL", "QSFP1_LPMODE" : "QSFP1_LPMODE", "SFP_01_TX_FAULT" : "SFP_01_TX_FAULT", "SFP_01_RX_LOS" : "SFP_01_RX_LOS", "SFP_01_MOD_ABS" : "SFP_01_MOD_ABS", "SFP_01_TX_DISABLE" : "SFP_01_TX_DISABLE", "SFP_01_RS0" : "SFP_01_RS0", "SFP_01_RS1" : "SFP_01_RS1", "SFP_02_TX_FAULT" : "SFP_02_TX_FAULT", "SFP_02_RX_LOS" : "SFP_02_RX_LOS", "SFP_02_MOD_ABS" : "SFP_02_MOD_ABS", "SFP_02_TX_DISABLE" : "SFP_02_TX_DISABLE", "SFP_02_RS0" : "SFP_02_RS0", "SFP_02_RS1" : "SFP_02_RS1", "SFP_03_TX_FAULT" : "SFP_03_TX_FAULT", "SFP_03_RX_LOS" : "SFP_03_RX_LOS", "SFP_03_MOD_ABS" : "SFP_03_MOD_ABS", "SFP_03_TX_DISABLE" : "SFP_03_TX_DISABLE", "SFP_03_RS0" : "SFP_03_RS0", "SFP_03_RS1" : "SFP_03_RS1", "SYSCTLR_JTAG_S1" : "SYSCTRL_MIO27_JTAG_S1", "SYSCTLR_JTAG_S0" : "SYSCTRL_MIO26_JTAG_S0", "SYSCTLR_VERSAL_MODE3" : "SYSCTRL_MIO41_DUT_MODE3", "SYSCTLR_VERSAL_MODE2" : "SYSCTRL_MIO40_DUT_MODE2", "SYSCTLR_VERSAL_MODE1" : "SYSCTRL_MIO39_DUT_MODE1", "SYSCTLR_VERSAL_MODE0" : "SYSCTRL_MIO38_DUT_MODE0", "SYSCTLR_VERSAL_MODE3_READBACK_RO" : "SYSCTRL_MIO45_MODE3_Rdbk", "SYSCTLR_VERSAL_MODE2_READBACK_RO" : "SYSCTRL_MIO44_MODE2_Rdbk", "SYSCTLR_VERSAL_MODE1_READBACK_RO" : "SYSCTRL_MIO43_MODE1_Rdbk", "SYSCTLR_VERSAL_MODE0_READBACK_RO" : "SYSCTRL_MIO42_MODE0_Rdbk", "SYSCTLR_POR_B_LS" : "SYSCTRL_MIO30_DUT_POR", "SYSCTLR_VERSAL_POR_B_READBACK_RO" : "SYSCTRL_MIO46_DUT_POR_Rd", "VERSAL_ERROR_OUT_LS_RO" : "SYSCTRL_MIO28_DUT_ERR_Rd", "VERSAL_DONE_RO" : "SYSCTRL_MIO29_DUT_DONE" }, "FMCs" : { "FMC" : { "Name" : "FMC", "I2C_Bus" : "/dev/i2c-0", "I2C_Address" : "0x50", "Presence_Labels" : ["FMCP1_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B"], "Supported_Volts" : [1.2], "Voltage_Regulator" : "VADJ_FMC", "Default_Volt" : 1.2, "Access_Label" : "I2C0_SW_SEL", "Access_Level" : 0 } }, "Boot Config" : { "PDI" : "system_wrapper.pdi", "ImageID" : "0x18700000", "UniqueID_Rev0" : "0x584c4e58" }, "BITs" : { "BIT_IDCODE_VERIFY" : { "Name" : "IDCODE Verify", "Description" : "This test verifies Versal silicon device ID code. The test failure means it is not a compatible device.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "XSDB_BIT", "TCL_File" : "idcode_verify.tcl 0x01" } } }, "BIT_EFUSE_VERIFY" : { "Name" : "EFUSE Verify", "Description" : "This test verifies the eFuse data matches the factory defaults. The test failure might be due to a non-compatible device or some eFuses have been set.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "XSDB_BIT", "TCL_File" : "read_efuse.tcl" } } }, "BIT_CLOCKS_OUTPUT_TEST" : { "Name" : "Clocks Output Test", "Description" : "This test verifies the clock output frequencies by measuring the clocks at the Versal with clock counters. The test will fail in case the clock settings are different than default values.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "XSDB_BIT", "TCL_File" : "versal_bit_download.tcl 0x1" } } }, "BIT_DDRMC_1_CAL_TEST" : { "Name" : "DDRMC_1 Cal Test", "Description" : "This test verifies Versal DDR memory controller 1 successfully completed calibration.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "DDRMC_1_Test" } } }, "BIT_DDRMC_2_CAL_TEST" : { "Name" : "DDRMC_2 Cal Test", "Description" : "This test verifies Versal DDR memory controller 2 successfully completed calibration.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "DDRMC_2_Test" } } }, "BIT_DDRMC_5_CAL_TEST" : { "Name" : "DDRMC_5 Cal Test", "Description" : "This test verifies Versal DDR memory controller 5 successfully completed calibration.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "DDRMC_5_Test" } } }, "BIT_DDRMC_6_CAL_TEST" : { "Name" : "DDRMC_6 Cal Test", "Description" : "This test verifies Versal DDR memory controller 6 successfully completed calibration.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "DDRMC_6_Test" } } }, "BIT_DRAM_MEM_TEST" : { "Name" : "DRAM Mem Test", "Description" : "This test verifies DRAM access by 8MB write, read and compare with cache on/off. The patterns used are 0s, 1's, 0xAAAA5555, row, col, bank.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "XSDB_BIT", "TCL_File" : "versal_bit_download.tcl 0x4" } } }, "BIT_OSPI_TEST" : { "Name" : "OSPI Test", "Description" : "This test verifies OSPI Flash read/write (non-destructive). The test operation consists of save first sector (4K byte) data, erase, write random data, read, compare and restore the original data. Warning!! This might corrupt OSPI memory in case the test fails.", "Manual" : 0, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "XSDB_BIT", "TCL_File" : "versal_bit_download.tcl 0x5" } } }, "BIT_PL_UART_TEST" : { "Name" : "PL UART Test", "Description" : "This test verifies PL UART and requires manual verification. The test performs by printing Hello world to PL UART port. It requires USB/jtag connection connected to a terminal application.", "Manual" : 1, "BIT Levels" : { "Level 0" : { "Plat_BIT_Op" : "XSDB_BIT", "TCL_File" : "versal_bit_download.tcl 0x106", "Instruction" : "\n1- Click on 'HOME >> VERSAL DEVICE CONTROL >> Versal UART Connection >> PL UART 0: Connect' and another browser tab will open connecting to PL UART 0 console.\n2- After clicking 'OK', go to other tab to view console output.\n" }, "Level 1" : { "Plat_BIT_Op" : "XSDB_BIT", "TCL_File" : "versal_bit_download.tcl 0x206", "Instruction" : "\n1- Test prints 'Hello world!' message to the PL UART console.\n2- Click 'Pass' if you observe the 'Hello world!' on the console.\n" } } } } } }